Job Description

General Summary:

Working as a part of Qualcomm System Infrastructure IP Verification team, contribute to full verification lifecycle, from system-level concept to tape out and post-silicon debug. The responsibility of the position involves comprehensive pre-silicon test planning for Infrastructure IP's such as high speed coherent, non-coherent interconnects and power management units, its testbench development using the advanced verification methodology such as SystemVerilog UVM, coverage development, assertion model development and perform verification closure. Co-ordinate requirements for verification, perform verification testplan reviews and verification signoff working with hardware design, architecture, and software teams. Perform formal verification (property checking), develop formal assumption models and checkers. Deploy Power-Aware UPF verification flow and methodology. Perform interop verification of Coherent Interconnects, Memory management units, TLB’s, CPU’s, Memory Controller, and Power management IP’s. Develop and deploy hardware platforms to perform software driver validation and accelerate functional simulation. Develop simulation VIP’s and deploy across projects. Involve in developing automation to improve verification efficiency. Opportunity to learn and experience complex and new protocols such as CXL, ARM CHI and more.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, or related work experience.

Minimum 5 years of experience in Design Verification domain. Preferred 10+ years of experience.
Experience with IP and/or System Level Testplan development
Experience in block-level and/or System Level testbench environment development
Experience in advance verification methodology such as SystemVerilog UVM or OVM or VMM
Experience in functional coverage development, code coverage, functional coverage closure and enable verification signoff.
Experience working with Emulation or Simulation Acceleration hardware platforms to validate software drivers and accelerate functional simulation
Experience working with RTL languages such as SystemVerilog or Verilog, or VHDL.
Strong knowledge of Cache Coherency, Memory Consistency, Memory Management unit for Virtualization
Strong knowledge of Object-oriented programming concepts including C or C++ programming skills
Strong debugging skills including RTL and Gate-Level design bugs
Preferred experience in simulation VIP development
Preferred experience in Formal Verification including developing SVA based Assertions IP and working with Formal Property Checking Tools
Preferred experience in Power Aware Verification including strong understanding of UPF specification
Preferred knowledge of ARM based bus protocols such as CHI or ACE or AXI/AHB/APB or CXS
Preferred knowledge of CXL and/or PCIe protocols
Preferred knowledge of Operation System Concepts
Preferred experience working on Embedded-C Code development to bring up CPU in System in Simulation and/or Hardware Platforms
Preferred experience with scripting and automation tool development using Perl or Python or C
Ability to adapt and consume new design features during any phase of verification stage
Ability to work in a team environment, manage own tasks on daily basis, meet goals on time, provide periodic project execution updates on week-to-week basis
Bachelor’s or Master’s degree in Computer Science, Electrical Engineer, Computer Engineering, or a closely related field