Job Description

We are seeking a Senior Electrical Engineer II responsible for application specific integrated circuit (ASIC) hardware security research and development. Responsibilities to include ASIC architecture, hardware security design, analysis, simulation, test, and integration of zero trust Analog, Mixed-Signal, and Digital Integrated Circuits for Raytheon Intelligence & Space. Must be an industry or academic leader in ASIC hardware security architecture and design with published journal articles and conference presentations. Must have simulation and prototyping knowledge and experience with advanced semiconductor node process design kits (PDKs), field programmable gate array (FPGA) firmware development, and algorithm development. Must be capable of functioning in multi-disciplined design teams across multiple projects.

Duties may also include serving as a hardware security design subject matter expert, technical leadership and oversight of design projects, new business proposal efforts, technical risk assessments, improvement of design processes, technology planning and mentoring.

The candidate is expected to work well on his or her own with minimal direction, Additionally, the applicant is expected to possess excellent problem solving skills, have strong written and verbal communication skills, be customer focused and organized.

Required Skills:

* Experience architecting, designing, and simulating security infrastructure or IP cores for ASICs.
* Experience performing hardware threat analyses, security and risk analyses.
* Experience with emulation and FPGA prototyping
* Experience with ASIC bring-up and post silicon validation
* Technical paper writing and presentation skills
* Hardware description languages (Verilog, System Verilog)
* Knowledge of IC design flows including analog, mixed-signal and digital ASIC design methodologie
* Knowledge of ASIC fabrication flow and Department of Defense (DoD) zero trust microelectronics roadmaps and initiatives
* Experience with secure boot, firmware, cryptographic algorithms, Physical Unclonable Function (PUF) and/or other chip fingerprinting technique

Desired Skills:

* Excellent communication and leadership skills
* Self-starter with initiative and independent judgment
* Ability to work well in a team environment virtual and in-person
* Capable of functioning in multi-disciplined design teams across multiple projects
* Ability to interface with program office and customer communities to define and ensure program objectives are achieved
* Work with department leadership team to develop and manage technology roadmaps in support of future technologies and IR&D. Provide technical, cost, and schedule data in support of proposals.

Required Education:

Major: Engineering EE or similar technical degree preferred

Degree/Experience: BS and 6 years of experience, MS and 4 years of experience, PhD and 2 years of experience.

This position requires either a U.S. Person or a Non-U.S. Person who is eligible to obtain any required Export Authorization.
U.S. Citizenship status is required as this position will need a U.S. Security Clearance within 1 year of start date.

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