Job Description

Job Description

This position is for an Analog Design Engineer in the IP Engineering Group (IPG) Technologists Office who will participate in the assessment of process technology collaterals encompassing simulation and layout domains. Responsibilities also include collaborating with Analog Mixed-Signal IP teams and other partner groups on diverse needs including but not limited to simulation data, test bench creation, understanding layout design rules, and running layout verification. We are seeking an individual who has strong technical knowledge in circuit simulations, analog design and validation, as well as basic understanding of layout design and rules. Candidates must also possess strong initiative, analytical/problem solving skills, and an ability to work in a diverse team environment.

As an Analog Design Engineer, responsibilities include, but are not limited to:

* Working closely with senior team members on analog device benchmark data generation including running functional simulations and variation (Monte Carlo) analysis

* Reviewing the results with other team members and designers and drawing conclusions

* Creating and/or migrating test benches from one technology node to another

* Working with design environment support teams to enable simulations when process technology collaterals or tools are updated

* Engaging with senior team members to learn Intel-specific layout design rules, running layout verification regression tests, comparing results, and drawing conclusions on changes

In addition to the qualifications listed below, the ideal candidate will also have:

* Excellent communications skills, both written and spoken

* Strong interpersonal skills to work effectively with a diverse group of partners and in demanding environment

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences. This is an entry level position and will be compensated accordingly.

Minimum Qualifications:

The candidate should possess a Master's degree in Electrical Engineering with 3+ months experience in:

* Solid understanding of semiconductor physics and analog/ mixed signal circuit design

* Hands-on experience in circuit simulation

* Understanding of silicon layout

Preferred Qualifications:

* Analog design simulation skills with industry standard design automation tools (e.g., Cadence Design Systems ADE/Maestro, Spectre, Virtuoso)

* Strong knowledge in CMOS semiconductor device physics with relevant coursework in CMOS digital, analog, and I/O circuit design

* Experience with layout verification, including design rule checks, connectivity checks, density checks, etc.

* Scripting experience with Perl or Python and a proficiency in Unix/Linux, including command shell

* Experience analyzing circuit reliability is a plus - for example, electrical overstress, electro-migration, self-heat, circuit aging, electrostatic discharge (ESD)
Inside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Folsom;US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

USCollege GradJR0156644Phoenix