Job Description

Job Description

We are looking for passionate and innovative engineers to join a world class power management team for Intel Xeon post silicon validation engineering group. This organization will be pushing advanced power management algorithms in high end servers to deliver cutting edge performance in AI, high performance computing and emerging data science workloads. Candidates will need to drive systematic debug of complex failures at system level, design experiments to root cause the issues and coordinate with different teams for execution of experiments. Candidates will also characterize and optimize power management architectures against various workloads to improve performance, identify weaknesses and help drive the direction of new power management ideas in next generation servers.

We seek engineers that are creative and can drive new techniques and software content to optimize debug processes, expand optimization search space and enable a deeper understanding of the system.

In addition to the qualifications listed below, the ideal candidate will also have:

* Strong initiative

* Problem solving/debug skills

* Communication skills

* Willingness to work within a diverse team environment

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must have a Master's degree in Electrical Engineering or Computer Engineering.

3+ years of experience with:

* Power management (DVFS, dynamic clocking and low power states) and power/thermal (Cdyn, leakage, power delivery, thermal margin)

* SOC level flows and deep understanding of one or more of the following domains: CPUs, IOs (PCIe), coherency, microcontroller debug, clocking, reset and hardware/firmware.

* Power/performance architecture and tuning including cache coherency protocols, prefetcher tuning and performance bottleneck analysis using EMON or performance counter monitors

Preferred Qualifications:

* Experience with system bring up, complex SoC sightings, root cause isolation and debug methodology and tools (JTAG, OSC/LA, on chip trace)

* Experience in Python/C/C++ SW programming for content development and scripting

* Experience with server and client-specific industry benchmarks and their application to measurement and competitive analyses of performance KPI's
Inside this Business Group
The everyday contributions of the Intel Validation Engineering (iVE) team are essential to retaining/regaining Intel's product leadership. We validate, debug, and tune the newest designs and world-changing technologies that enrich the lives of every person on earth. We play a critical role in completing the PRQs of Intel products and in Intel's ability to deliver the annual technology platforms in our roadmap.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

USExperienced HireJR0149443Santa Clara