Job Description

Job Area:

Engineering Group, Engineering Group > Packaging Engineering

General Summary:

Overview

This position is a key member of Qualcomm’s Integrated Circuits (IC) package engineering team and offers an opportunity to impact Qualcomm's current and future chipsets. Using FEA expertise and working closely with design, New Product Introduction (NPI) and Chip-Package Interaction (CPI) teams this role provides mechanical simulation support for current HVM and advanced packaging technologies.

Success in this position requires engineering expertise in developing mechanical FEA models (preferably using ANSYS APDL), maintaining ANSYS macros/workflows, establishing FEA methodologies and BKM for test correlation, material characterization, and performing stress analysis, mechanical analysis and failure prediction of IC package designs.

Responsibilities of this role include warpage and stress analysis, solder joint reliability (SJR) prediction, package/module assembly process simulation, and CPI analysis for various silicon nodes (BEOL) and requires the capability of using advanced Finite Element Analysis (FEA) techniques (sub-modeling approach, contact analysis, non-linear analysis), creating novel FEA approaches and expanding internal prediction capabilities.

Effectiveness requires a thorough understanding of the fundamentals of silicon, package, SiP/Module, and board level interconnect technologies as well as a demonstrated project focus and exceptional communication and execution skills.

This is an individual contributor role ideally for an experienced, highly motivated self-starter committed to product success who is looking to own and lead solving complex thermo-mechanical challenges between SoCs and SiP/module programs.

Minimum Qualifications:

• Master’s degree in Mechanical engineering, Material science, Electrical/Microelectronics, or related engineering field.
• 9+ years of work experience in mechanical FEA analysis in semiconductor and IC microelectronic packaging.
• 7+ years of experience in ANSYS (APDL and Workbench)

Preferred Qualifications

Ph.D. in Mechanical Engineering, Material Science, Electrical Engineering, Microelectronics or related engineering field.
10+ years of work experience in mechanical FEA analysis for Semiconductor and IC microelectronic packaging. Hands-on experience with various IC electronic packaging structures, SiP/Module structures, assembly processes, reliability testing and analysis, CPI, BLR and design of experiments (DOE).
10+ years of experience in ANSYS (APDL and Workbench)
Solid understanding of IC packaging materials and their thermo-mechanical behaviors.
FEA experience with large SiP/Modules, FCBGA packages (bare-die vs lidded), thermo-mechanical behavior/interaction of TIM/Lid/adhesive and its predictions are preferred.
Hands on FEA experience in Automotive/Datacenter SoC package applications or SiP/module applications.
Research and publication in FEA predictive modeling, Warpage, CPI, and Solder lifetime prediction.
Excellent analytical and project execution skills.
Experience leading complex analyses and making impactful decisions.
Excellent communication and presentation skills.