Job Description

Job Description

This position is within the Design Enablement (DE) organization of Technology Development (TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. The Programable Electrical Rule Checks (PERC) electrostatic discharge (ESD) development team within this organization is looking for individuals who will be responsible to develop PERC ESD rule decks for latest Intel technologies. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies.

Responsibilities:

* Development of ESD/LU rule decks based on Design Rule Manual (DRM) requirements
* Creating reliability ESD and LU design rules specifications
* Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specification
* Test-cases creation for debugging and validation
* Define requirements for QA and related automation
* Drive innovation and initiatives to enhance existing automation, tools and methodology
* Identify and analyze problems, plans, tasks and solutions

The candidate should also exhibit the following behavioral traits and/or skills:

* Ability to work in a dynamic and team-oriented environment
* Creative, independent and out of the box thinker with strong problem-solving skills and analytical ability.
* Attention to details, strong organization skills
* Depth and Breadth being able to connect the dots and identify cross-discipline optimal solutions
* Self-motivated, strong leadership skills being able to influence across internal and external ecosystem
* Written and verbal communication skills to present complex issues with clarity to drive decisions
* Ability to work with cross-functional and cross site teams and influence multiple internal and external stakeholders

Qualifications

You must possess minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualification

MS in EE/CE/ECE with 2+ years of industry experience or PhD in EE/CE/ECE with 1+ year of industry experience in the areas below

Areas of experience:

* Hands on experience with Calibre and ICV PERC tools
* ESD/LU Pre-Si models (HBM and CDM), I/O design and methodologies
* Debugging skills
* Experience in runsets, extraction and physical design domain
* Experience in scripting languages for QA automation
* Experience in driving cross-functional and industry wide initiatives and taskforces
* Knowledge of semiconductor device physics, process technology, and design rules

Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth

Other Locations

US, Arizona, Phoenix;US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

USExperienced HireJR0157648Hillsboro