Job Description

Company:

Qualcomm Technologies International Ltd

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

Job Overview:

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.

Based in our Cambridge office as a key contributor on the implementation of mixed signal chips with a focus on digital place and route, clock tree design along with physical and timing closure.

In your role as a key contributor to the physical implementation you will have an understanding of the Place and Route of a digital block or chip and a working knowledge of low power design methodologies (e.g. UPF/CPF), and their impact on a physical implementation flow.

Successful candidates will have a track record in delivery of digital cores or chips through a final sign-off.

Key Responsibilities:

Key contributor for physical implementation.

* Running place and route tools and achieving timing closure.
* Building clock trees and feeding back design changes to improve physical results.
* Building chip level floorplans including macro placements and padrings.
* Helping support and develop tool flows.

Please note, this is a Senior Engineer role so we are looking for Engineers with 4+ years of relevant experience

Minimum Qualifications:

* Experience of one or more of floor planning, place and route, clock tree design along or physical and timing closure.
* Practical experience of the associated EDA tools.
* Understanding of key scripting languages particularly TCL.
* Experience of working as part of a larger team and working to project milestones and deadlines.
* Good team worker acting as a mentor for the junior team members and working with the wider design teams to support their efforts.

Preferred Qualifications:

* Experience of at least two areas of implementation from floorplanning, place and route, clock tree design or physical and timing closure
* Library and Macro preparations for place and route.
* Proficient in scripting languages (e.g. Python, Perl, TCL)
* Experience of Low Power Design methodologies especially power gating.
* Understanding of synthesis and test tools and their impact on the flow.
* Use of bug-tracking and revision control systems

Educational Requirements:

* Degree (or equivalent qualification) in maths/science/electronics

Keywords:

STA, place and route, DRC,LVS,floorplanning,PNR,clock tree, timing closure, low power, physical design, layout,digital physical design, CTS

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

Applicants: If you are an individual with a disability and need an accommodation during the application/hiring process, please call Qualcomms toll-free number found here for assistance. Qualcomm will provide reasonable accommodations, upon request, to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm is an equal opportunity employer and supports workforce diversity.

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