Job Description

Facebook is hiring ASIC Power Engineers within our Infrastructure organization to work on low level power designs. We are looking for individuals with experience in power modeling for ASICs (architecture to silicon), developing flows around EDA tools, and low-power design to build efficient System on Chip (SoC) and IP for data center applications.

ASIC Engineer, Power Responsibilities

* Define the power specification at system and module level for Idle, TDP, Typical use cases.

* Develop power modeling infrastructure in Python/C++.

* Work with or develop architectural simulators in order to model performance and power.

* Build power estimation flows at various levels of abstraction: C-model, RTL, Gate, Layout.

* Optimize design for low-power with the understanding of system level concepts.

* Evaluation and Implementation of low-power design techniques at different levels of abstraction.

* Power characterization on silicon: idle, TDP, use case power & debug power issues on silicon.

* Partner with vendors to drive low-power requirements for SoC interfaces such as LPDDR, PCIe, etc. Partner with EDA tool vendors to select and deploy the appropriate power estimation tools.

* Collaborate with internal HW/SW Co-design, Architecture, Design, DV, and Emulation teams for power flows, optimization and estimation.

Minimum Qualifications

* B.S. or M.S. degree in Computer Engineering, Computer Science or Electrical Engineering

* Understanding of ASIC design process and knowledge of leakage and dynamic power, and impact of environment and manufacturing process on power

* Experience with modeling and design with C++/Python or an equivalent high level language

* Knowledge of front-end and back-end ASIC tools

* Experience with RTL design using SystemVerilog or other HDL

* Experience managing multiple design releases and working with cross functional teams to support and debug power issues

* Experience with EDA tools and scripting languages (Python, Tcl) used to build tools and flows for complex environments

* Experience with communicating across functional internal teams and with vendors

Preferred Qualifications

* Experience with architectural performance and power models at SoC and system level

* Low-power design techniques such as clock-gating, power-gating, DVFS, AVS

* Experience architecting systems for various design scales (IP blocks, SOC, multi-chip system) with an understanding of tradeoffs between performance and power

* Post-silicon bringup, debug and identify issues on emulator and RTL

Locations

About the Facebook company

Facebook's mission is to give people the power to build community and bring the world closer together. Through our family of apps and services, we're building a different kind of company that connects billions of people around the world, gives them ways to share what matters most to them, and helps bring people closer together. Whether we're creating new products or helping a small business expand its reach, people at Facebook are builders at heart. Our global teams are constantly iterating, solving problems, and working together to empower people around the world to build community and connect in meaningful ways. Together, we can help people build stronger communities we're just getting started.

Facebook is committed to providing reasonable support (called accommodations) in our recruiting processes for candidates with disabilities, long term conditions, mental health conditions or who are neurodivergent, and to candidates with sincerely held religious beliefs or requiring pregnancy related support. If you need support, please reach out to accommodations-ext@fb.com.