Job Description

Job Description

* In this position, you will be working within the Fabric IP team to deliver configurable interconnect fabric designs
Our design team works in close partnership with validation and automation allowing us to deliver flexible designs that are used everywhere from low power IoTG to high end server applications We deliver all across Intel giving the team impact and exposure to different projects
Responsibilities include but not limited to:
* Evaluating new archuArch requirements
* Writing and testing new RTL
* Resolving timing paths
* Debugging customer SOC failures
* Running design checking tools
* Making quarterly releases of new IP

Qualifications

Must have Master's degree in Electrical / Computer Engineering with 8+ years of direct hands-on work experience in

* Frontend RTL design
* Validation and scripting Analysis and development of RTL to meet architecture requirements
* Ability to make tradeoffs of area schedule power performance
* Ability to create from scratch or leverage existing IP as needed
* RTL coding Verilog system Verilog logic simulation synthesis and timing analysis
* Experience with design tools Lint Synthesis CDC FV ATPG etc
* Strong written and communication skills are essential since our team delivers to many internal customer groups that we support in deployment
Preferred requirements:
* Knowledge of various bus protocols async crossing techniques clock gating challenges
* Experience working with cross functional and cross site teams
* Experience creating and debugging scripts Python TCL

Inside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

USExperienced HireJR0161023Santa Clara