Job Description

Job Description

The candidate will be part of a silicon design team chartered with developing and delivering multiple generations of state of the art, highly configurable upstream and downstream Compute Express Link (CXL) cache and Mem IPs to multiple Intel server and client SOCs.

Key responsibilities of the role include, although not limited to:

* Develop validation environments including checkers, monitors and test suites-

* Execute test plans by writing random and pseudo random stimulus and directed tests. Driving functional and code coverage-

* Debug failures on simulati / emulation / post silicon, file bugs and validate fixes-

* Feature evaluations for colexity and effort working with design and architecture team, writing test plans-

* Participate in improvements to the validation environment that drive down validation escape bug rates-

* Supporting debug of failures for customers

The role requires the following attributes:

* Hands-on verification experience and proficiency using System Verilog and strong proficiency using OVM/UVM.

* Proven track record in pre-silicon verification from environment development to test development.

* Ability to work in a dynamic environment with abstract requirements.

* Very good problem solving skills.

* Experience with implementation and use modern verification environments that include use of constrained-random stimulus and use of functional coverage.

* Experience with link layer based designs and protocols like PCIe is highly desired, but not a must-have.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Candidate must have a Bachelor's degree in Electrical/Computer Engineering and 6+ years of experience in: - OR - a Master's degree in Electrical/Computer Engineering and 4+ years of experience in:

* Reading and interpreting technical specs and Register Transfer Level (RTL) code.
* Experience with IP / SoC development, verification using System Verilog/ OVM / UVM.
* Debug, writing monitors/checkers/reference models / stimulus
* Using simulation/debug tools like VCS / Verdi

Preferred skills include:

* Writing validation plans and software to implement those validation plans.
* IO protocols like PCIe / CXL etc.
* Coherency and protocols like IDI / UPI
* Programming and scripting with C/C++/Perl/Python

Inside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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