Job Description

Job Description

Intels Xeon Silicon Design (XSD organization) is looking for SOC Verification Engineer Pre-Silicon with expertise in Simulation/Emulation Verification of SOCs. The candidate will be responsible for verification execution at SOC level, driving efficiencies in verification strategies by taking a holistic view starting from planning, architecture, design, verification and production.

In this role of owning specific domain for Simulation and/or Emulation at SOC, you will be responsible for of the following

* SOC Verification and Validation strategies for future and tactical approaches for current generation to enable successful Tape-In with zero Post-Silicon Bugs.
* Working with the RTL and Verification technical leads in a hands on fashion and help shape the next generation IP, Sub-System and SOC Verification methodologies and processes.
* Technical assessment of IP and feature asks and recommendations to management of the complexity and risk profiles.
* Drive Logic and Verification methodologies as well as tool flows and future intercepts.
* Proven track record of active engagement and technical delivery of high quality complex ASICs/SOCs or IPs across multiple design generations is required.

The ideal candidate should exhibit the following behavioral traits:

* Strong demonstration of ability to innovate
* Ability to work with teams across projects, domains and Geos
* Self-starter, self-motivator, and highly adaptable

Qualifications

Minimum Qualifications

A bachelor's degree in Electrical/ Electronics/Computer Engineering, Computer Science with or related field with 6+ years of experience. Or a master's degree with 4+ years of experience.

Your experience will be in the following:

* Must have advanced understanding of the technical validation concepts, architecture, systems, development methods and disciplines associated with the program and utilize knowledge to accelerate the program's completion.
* Experience with Logic Design verification
* Experience with pre-Silicon simulation/emulation tool flows required
* Example tools include but not limited to:- Synopsys VCS, Verdi and DVE
* Knowledge of UVM, OVM, System Verilog, C, C++, Python for developing verification test benches and constrained random validation.

Inside this Business Group
Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Other Locations

US, Oregon, Hillsboro

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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