Job Description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

Job Overview:

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.

Low power design engineers are responsible for thoroughly understanding the Low Power Architecture of the GPU including the clocking and reset architecture and come up with uArch specifications and implement the design and ensure successful validation and commercialization of all low power features.

Ownership and Responsibilities

Work very closely with GPU and SOC power Architecture teams and carefully understand the requirements for a particular product and translate that understanding to uArch and design specifications and participate in high level reviews.

Work very closely with power implementation teams to ensure the low power specifications are thoroughly understand and implemented by the Si implementation teams.

Work very closely with Design Verification teams to review and sign off the validation of all low power and clocking features across products.

As part of Si bring up the Engineers are expected to work with post Si validation and power SW teams and system performance/thermal teams to ensure all low power features are successfully productized and be the primary point of contact for all HW low power queries/debugs

Expected to work on power estimation and optimization analysis as part of continuous efforts to look for power optimization opportunities.

Qualifications:

* Experience in Low power design with very good understanding of ASIC Low power Architecture and low power concepts and very good understanding of ASIC systems in general.
* Experience with hardware design (Verilog/System Verilog) with emphasis on clocking/reset and power sequencers
* Good understanding of Power Intent( UPF) and prior experience in power estimation and optimization using PTPX/Power Artist is desired
* Ability to work with several cross functional teams. Self driven and ability to methodically overcome challenges.
* Bachelors/Master's degree in Electrical/Electronics Engineering, Computer Science, or related field
* Minimum 3-4 years of experience in front end design and very good understanding of all front end tool flows

Applicants: If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email to accommodationsupport

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