Job Description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

Job Overview:

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.

Job Overview:

Looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for mobile space.

Participate on a project involved in the development of ASICs, with emphasis in synthesis, timing closure, low power, place and route.
Develop constraints, run physical synthesis, low Power checks, timing and power analysis.
Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward
Work closely with RTL design, physical design, low power and automation teams to optimize performance and power
Generate, review and validate design constraints to achieve timing closure of High-speed cores.
Tabulate metrics results for analysis comparison
10-15 years of Synthesis and ASIC design work experience
Extensive experience in Synthesis with DCT/DCG or RC/RCP/Genus an absolute must.
Complete ASIC flow with low power, performance and area optimization techniques
Experience with STA using Primetime and PTPX required
Proficient in constraint generation
Experience of multiple power domain implementation with complex UPF/CPF definition required
Formal verification experience (Formality/Conformal)
Perl/Tcl scripting is required
Strong problem solving and ASIC development/debugging skills
Experience with CPU micro-architecture and their critical path
Low power implementation techniques experience
High speed CPU implementation
Place and route tool experience
Constraint management tool and Verilog coding experience

Extensive experience in Synthesis with DCT/DCG or RC/RCP/Genus an absolute must.
Complete ASIC flow with low power, performance and area optimization techniques
Experience with STA using Primetime and PTPX required
Proficient in constraint generation
Experience of multiple power domain implementation with complex UPF/CPF definition required
Formal verification experience (Formality/Conformal)
Perl/Tcl scripting is required
Strong problem solving and ASIC development/debugging skills
Experience with CPU micro-architecture and their critical path
Low power implementation techniques experience
High speed CPU implementation
Place and route tool experience
Constraint management tool and Verilog coding experience

Applicants: If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email to accommodationsupport

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